`ifndef UDLY
`define UDLY 1
`endif
module fft_tb__1(

);
//parameter declare
//port declare
//channel declare
logic fft_ch__fft_cfg__start;
logic fft_ch__sram__0__valid;
logic fft_ch__sram__0__ready;
logic fft_ch__sram__0__we_n;
logic [31:0] fft_ch__sram__0__addr;
logic [63:0] fft_ch__sram__0__wdata;
logic [63:0] fft_ch__sram__0__rdata;
logic fft_ch__instr_sram__valid;
logic fft_ch__instr_sram__ready;
logic fft_ch__instr_sram__we_n;
logic [31:0] fft_ch__instr_sram__addr;
logic [15:0] fft_ch__instr_sram__wdata;
logic [15:0] fft_ch__instr_sram__rdata;
logic fft_ch__exp_sram__valid;
logic fft_ch__exp_sram__ready;
logic fft_ch__exp_sram__we_n;
logic [31:0] fft_ch__exp_sram__addr;
logic [63:0] fft_ch__exp_sram__wdata;
logic [63:0] fft_ch__exp_sram__rdata;
logic [31:0] data_mem_port_ch__0__addr;
logic [63:0] data_mem_port_ch__0__wdata;
logic [63:0] data_mem_port_ch__0__rdata;
logic data_mem_port_ch__0__we_n;
logic data_mem_port_ch__0__ce_n;
logic [31:0] data_mem_port_ch__1__addr;
logic [63:0] data_mem_port_ch__1__wdata;
logic [63:0] data_mem_port_ch__1__rdata;
logic data_mem_port_ch__1__we_n;
logic data_mem_port_ch__1__ce_n;
logic [31:0] data_mem_port_ch__2__addr;
logic [63:0] data_mem_port_ch__2__wdata;
logic [63:0] data_mem_port_ch__2__rdata;
logic data_mem_port_ch__2__we_n;
logic data_mem_port_ch__2__ce_n;
logic [31:0] data_mem_port_ch__3__addr;
logic [63:0] data_mem_port_ch__3__wdata;
logic [63:0] data_mem_port_ch__3__rdata;
logic data_mem_port_ch__3__we_n;
logic data_mem_port_ch__3__ce_n;
logic [31:0] instr_mem_port_ch__mem_port__addr;
logic [15:0] instr_mem_port_ch__mem_port__wdata;
logic [15:0] instr_mem_port_ch__mem_port__rdata;
logic instr_mem_port_ch__mem_port__we_n;
logic instr_mem_port_ch__mem_port__ce_n;
logic [31:0] exp_mem_port_ch__mem_port__addr;
logic [63:0] exp_mem_port_ch__mem_port__wdata;
logic [63:0] exp_mem_port_ch__mem_port__rdata;
logic exp_mem_port_ch__mem_port__we_n;
logic exp_mem_port_ch__mem_port__ce_n;
logic mux_ch__mem_req__0__valid;
logic mux_ch__mem_req__0__ready;
logic mux_ch__mem_req__0__we_n;
logic [31:0] mux_ch__mem_req__0__addr;
logic [63:0] mux_ch__mem_req__0__rdata;
logic [63:0] mux_ch__mem_req__0__wdata;
logic mux_ch__mem__0__ce_n;
logic mux_ch__mem__0__we_n;
logic [31:0] mux_ch__mem__0__addr;
logic [63:0] mux_ch__mem__0__rdata;
logic [63:0] mux_ch__mem__0__wdata;
logic mux_ch__mem__1__ce_n;
logic mux_ch__mem__1__we_n;
logic [31:0] mux_ch__mem__1__addr;
logic [63:0] mux_ch__mem__1__rdata;
logic [63:0] mux_ch__mem__1__wdata;
logic mux_ch__mem__2__ce_n;
logic mux_ch__mem__2__we_n;
logic [31:0] mux_ch__mem__2__addr;
logic [63:0] mux_ch__mem__2__rdata;
logic [63:0] mux_ch__mem__2__wdata;
logic mux_ch__mem__3__ce_n;
logic mux_ch__mem__3__we_n;
logic [31:0] mux_ch__mem__3__addr;
logic [63:0] mux_ch__mem__3__rdata;
logic [63:0] mux_ch__mem__3__wdata;
logic instr_mux_ch__mem_req__0__valid;
logic instr_mux_ch__mem_req__0__ready;
logic instr_mux_ch__mem_req__0__we_n;
logic [31:0] instr_mux_ch__mem_req__0__addr;
logic [15:0] instr_mux_ch__mem_req__0__rdata;
logic [15:0] instr_mux_ch__mem_req__0__wdata;
logic instr_mux_ch__mem__0__ce_n;
logic instr_mux_ch__mem__0__we_n;
logic [31:0] instr_mux_ch__mem__0__addr;
logic [15:0] instr_mux_ch__mem__0__rdata;
logic [15:0] instr_mux_ch__mem__0__wdata;
logic instr_mux_ch__mem__1__ce_n;
logic instr_mux_ch__mem__1__we_n;
logic [31:0] instr_mux_ch__mem__1__addr;
logic [15:0] instr_mux_ch__mem__1__rdata;
logic [15:0] instr_mux_ch__mem__1__wdata;
logic exp_mux_ch__mem_req__0__valid;
logic exp_mux_ch__mem_req__0__ready;
logic exp_mux_ch__mem_req__0__we_n;
logic [31:0] exp_mux_ch__mem_req__0__addr;
logic [63:0] exp_mux_ch__mem_req__0__rdata;
logic [63:0] exp_mux_ch__mem_req__0__wdata;
logic exp_mux_ch__mem__0__ce_n;
logic exp_mux_ch__mem__0__we_n;
logic [31:0] exp_mux_ch__mem__0__addr;
logic [63:0] exp_mux_ch__mem__0__rdata;
logic [63:0] exp_mux_ch__mem__0__wdata;
logic exp_mux_ch__mem__1__ce_n;
logic exp_mux_ch__mem__1__we_n;
logic [31:0] exp_mux_ch__mem__1__addr;
logic [63:0] exp_mux_ch__mem__1__rdata;
logic [63:0] exp_mux_ch__mem__1__wdata;
//wire declare
//port wire declare
//register declare
//register init and update
logic clk;
initial begin
  clk = 1'h0;
end

logic rstn;
initial begin
  rstn = 1'h0;
end

//assign logic
assign mux_ch__mem__0__rdata /* 127 */ = data_mem_port_ch__0__rdata /* 127 */ ;
assign data_mem_port_ch__0__addr /* 127 */ = mux_ch__mem__0__addr /* 127 */ ;
assign data_mem_port_ch__0__wdata /* 127 */ = mux_ch__mem__0__wdata /* 127 */ ;
assign data_mem_port_ch__0__we_n /* 127 */ = mux_ch__mem__0__we_n /* 127 */ ;
assign data_mem_port_ch__0__ce_n /* 127 */ = mux_ch__mem__0__ce_n /* 127 */ ;
assign mux_ch__mem__1__rdata /* 127 */ = data_mem_port_ch__1__rdata /* 127 */ ;
assign data_mem_port_ch__1__addr /* 127 */ = mux_ch__mem__1__addr /* 127 */ ;
assign data_mem_port_ch__1__wdata /* 127 */ = mux_ch__mem__1__wdata /* 127 */ ;
assign data_mem_port_ch__1__we_n /* 127 */ = mux_ch__mem__1__we_n /* 127 */ ;
assign data_mem_port_ch__1__ce_n /* 127 */ = mux_ch__mem__1__ce_n /* 127 */ ;
assign mux_ch__mem__2__rdata /* 127 */ = data_mem_port_ch__2__rdata /* 127 */ ;
assign data_mem_port_ch__2__addr /* 127 */ = mux_ch__mem__2__addr /* 127 */ ;
assign data_mem_port_ch__2__wdata /* 127 */ = mux_ch__mem__2__wdata /* 127 */ ;
assign data_mem_port_ch__2__we_n /* 127 */ = mux_ch__mem__2__we_n /* 127 */ ;
assign data_mem_port_ch__2__ce_n /* 127 */ = mux_ch__mem__2__ce_n /* 127 */ ;
assign mux_ch__mem__3__rdata /* 127 */ = data_mem_port_ch__3__rdata /* 127 */ ;
assign data_mem_port_ch__3__addr /* 127 */ = mux_ch__mem__3__addr /* 127 */ ;
assign data_mem_port_ch__3__wdata /* 127 */ = mux_ch__mem__3__wdata /* 127 */ ;
assign data_mem_port_ch__3__we_n /* 127 */ = mux_ch__mem__3__we_n /* 127 */ ;
assign data_mem_port_ch__3__ce_n /* 127 */ = mux_ch__mem__3__ce_n /* 127 */ ;
assign fft_ch__sram__0__ready /* 127 */ = mux_ch__mem_req__0__ready /* 127 */ ;
assign fft_ch__sram__0__rdata /* 127 */ = mux_ch__mem_req__0__rdata /* 127 */ ;
assign mux_ch__mem_req__0__valid /* 127 */ = fft_ch__sram__0__valid /* 127 */ ;
assign mux_ch__mem_req__0__we_n /* 127 */ = fft_ch__sram__0__we_n /* 127 */ ;
assign mux_ch__mem_req__0__addr /* 127 */ = fft_ch__sram__0__addr /* 127 */ ;
assign mux_ch__mem_req__0__wdata /* 127 */ = fft_ch__sram__0__wdata /* 127 */ ;
assign fft_ch__instr_sram__ready /* 127 */ = instr_mux_ch__mem_req__0__ready /* 127 */ ;
assign fft_ch__instr_sram__rdata /* 127 */ = instr_mux_ch__mem_req__0__rdata /* 127 */ ;
assign instr_mux_ch__mem_req__0__valid /* 127 */ = fft_ch__instr_sram__valid /* 127 */ ;
assign instr_mux_ch__mem_req__0__we_n /* 127 */ = fft_ch__instr_sram__we_n /* 127 */ ;
assign instr_mux_ch__mem_req__0__addr /* 127 */ = fft_ch__instr_sram__addr /* 127 */ ;
assign instr_mux_ch__mem_req__0__wdata /* 127 */ = fft_ch__instr_sram__wdata /* 127 */ ;
assign fft_ch__exp_sram__ready /* 127 */ = exp_mux_ch__mem_req__0__ready /* 127 */ ;
assign fft_ch__exp_sram__rdata /* 127 */ = exp_mux_ch__mem_req__0__rdata /* 127 */ ;
assign exp_mux_ch__mem_req__0__valid /* 127 */ = fft_ch__exp_sram__valid /* 127 */ ;
assign exp_mux_ch__mem_req__0__we_n /* 127 */ = fft_ch__exp_sram__we_n /* 127 */ ;
assign exp_mux_ch__mem_req__0__addr /* 127 */ = fft_ch__exp_sram__addr /* 127 */ ;
assign exp_mux_ch__mem_req__0__wdata /* 127 */ = fft_ch__exp_sram__wdata /* 127 */ ;
//initial statement
initial begin
  $display("start sequence sequence__1083");
  #0
  rstn /* 48 */ = 0 /* 48 */ ;
  #100
  rstn /* 50 */ = 1 /* 50 */ ;
end

//forever statement
always begin
  #5
  clk /* 41 */ = !clk /* 41 */ ;
end

//cell instance
mem_model__2 data_mem_bank_0(
  .mem_port__addr( data_mem_port_ch__0__addr),
  .mem_port__wdata( data_mem_port_ch__0__wdata),
  .mem_port__rdata( data_mem_port_ch__0__rdata),
  .mem_port__we_n( data_mem_port_ch__0__we_n),
  .mem_port__ce_n( data_mem_port_ch__0__ce_n),
  .clk( clk ),
  .rstn( rstn )
);

mem_model__3 data_mem_bank_1(
  .mem_port__addr( data_mem_port_ch__1__addr),
  .mem_port__wdata( data_mem_port_ch__1__wdata),
  .mem_port__rdata( data_mem_port_ch__1__rdata),
  .mem_port__we_n( data_mem_port_ch__1__we_n),
  .mem_port__ce_n( data_mem_port_ch__1__ce_n),
  .clk( clk ),
  .rstn( rstn )
);

mem_model__4 data_mem_bank_2(
  .mem_port__addr( data_mem_port_ch__2__addr),
  .mem_port__wdata( data_mem_port_ch__2__wdata),
  .mem_port__rdata( data_mem_port_ch__2__rdata),
  .mem_port__we_n( data_mem_port_ch__2__we_n),
  .mem_port__ce_n( data_mem_port_ch__2__ce_n),
  .clk( clk ),
  .rstn( rstn )
);

mem_model__5 data_mem_bank_3(
  .mem_port__addr( data_mem_port_ch__3__addr),
  .mem_port__wdata( data_mem_port_ch__3__wdata),
  .mem_port__rdata( data_mem_port_ch__3__rdata),
  .mem_port__we_n( data_mem_port_ch__3__we_n),
  .mem_port__ce_n( data_mem_port_ch__3__ce_n),
  .clk( clk ),
  .rstn( rstn )
);

mem_model__6 exp_mem_u0(
  .mem_port__addr( exp_mem_port_ch__mem_port__addr),
  .mem_port__wdata( exp_mem_port_ch__mem_port__wdata),
  .mem_port__rdata( exp_mem_port_ch__mem_port__rdata),
  .mem_port__we_n( exp_mem_port_ch__mem_port__we_n),
  .mem_port__ce_n( exp_mem_port_ch__mem_port__ce_n),
  .clk( clk ),
  .rstn( rstn )
);

fft__7 fft_u0(
  .fft_cfg__start( fft_ch__fft_cfg__start),
  .sram__0__valid( fft_ch__sram__0__valid),
  .sram__0__ready( fft_ch__sram__0__ready),
  .sram__0__we_n( fft_ch__sram__0__we_n),
  .sram__0__addr( fft_ch__sram__0__addr),
  .sram__0__wdata( fft_ch__sram__0__wdata),
  .sram__0__rdata( fft_ch__sram__0__rdata),
  .instr_sram__valid( fft_ch__instr_sram__valid),
  .instr_sram__ready( fft_ch__instr_sram__ready),
  .instr_sram__we_n( fft_ch__instr_sram__we_n),
  .instr_sram__addr( fft_ch__instr_sram__addr),
  .instr_sram__wdata( fft_ch__instr_sram__wdata),
  .instr_sram__rdata( fft_ch__instr_sram__rdata),
  .exp_sram__valid( fft_ch__exp_sram__valid),
  .exp_sram__ready( fft_ch__exp_sram__ready),
  .exp_sram__we_n( fft_ch__exp_sram__we_n),
  .exp_sram__addr( fft_ch__exp_sram__addr),
  .exp_sram__wdata( fft_ch__exp_sram__wdata),
  .exp_sram__rdata( fft_ch__exp_sram__rdata),
  .clk( clk ),
  .rstn( rstn )
);

mem_model__8 instr_mem_u0(
  .mem_port__addr( instr_mem_port_ch__mem_port__addr),
  .mem_port__wdata( instr_mem_port_ch__mem_port__wdata),
  .mem_port__rdata( instr_mem_port_ch__mem_port__rdata),
  .mem_port__we_n( instr_mem_port_ch__mem_port__we_n),
  .mem_port__ce_n( instr_mem_port_ch__mem_port__ce_n),
  .clk( clk ),
  .rstn( rstn )
);

mem_mux__9 mux_u0(
  .mem_req__0__valid( mux_ch__mem_req__0__valid),
  .mem_req__0__ready( mux_ch__mem_req__0__ready),
  .mem_req__0__we_n( mux_ch__mem_req__0__we_n),
  .mem_req__0__addr( mux_ch__mem_req__0__addr),
  .mem_req__0__rdata( mux_ch__mem_req__0__rdata),
  .mem_req__0__wdata( mux_ch__mem_req__0__wdata),
  .mem__0__ce_n( mux_ch__mem__0__ce_n),
  .mem__0__we_n( mux_ch__mem__0__we_n),
  .mem__0__addr( mux_ch__mem__0__addr),
  .mem__0__rdata( mux_ch__mem__0__rdata),
  .mem__0__wdata( mux_ch__mem__0__wdata),
  .mem__1__ce_n( mux_ch__mem__1__ce_n),
  .mem__1__we_n( mux_ch__mem__1__we_n),
  .mem__1__addr( mux_ch__mem__1__addr),
  .mem__1__rdata( mux_ch__mem__1__rdata),
  .mem__1__wdata( mux_ch__mem__1__wdata),
  .mem__2__ce_n( mux_ch__mem__2__ce_n),
  .mem__2__we_n( mux_ch__mem__2__we_n),
  .mem__2__addr( mux_ch__mem__2__addr),
  .mem__2__rdata( mux_ch__mem__2__rdata),
  .mem__2__wdata( mux_ch__mem__2__wdata),
  .mem__3__ce_n( mux_ch__mem__3__ce_n),
  .mem__3__we_n( mux_ch__mem__3__we_n),
  .mem__3__addr( mux_ch__mem__3__addr),
  .mem__3__rdata( mux_ch__mem__3__rdata),
  .mem__3__wdata( mux_ch__mem__3__wdata),
  .clk( clk ),
  .rstn( rstn )
);

mem_mux__10 mux_u1(
  .mem_req__0__valid( instr_mux_ch__mem_req__0__valid),
  .mem_req__0__ready( instr_mux_ch__mem_req__0__ready),
  .mem_req__0__we_n( instr_mux_ch__mem_req__0__we_n),
  .mem_req__0__addr( instr_mux_ch__mem_req__0__addr),
  .mem_req__0__rdata( instr_mux_ch__mem_req__0__rdata),
  .mem_req__0__wdata( instr_mux_ch__mem_req__0__wdata),
  .mem__0__ce_n( instr_mux_ch__mem__0__ce_n),
  .mem__0__we_n( instr_mux_ch__mem__0__we_n),
  .mem__0__addr( instr_mux_ch__mem__0__addr),
  .mem__0__rdata( instr_mux_ch__mem__0__rdata),
  .mem__0__wdata( instr_mux_ch__mem__0__wdata),
  .mem__1__ce_n( instr_mux_ch__mem__1__ce_n),
  .mem__1__we_n( instr_mux_ch__mem__1__we_n),
  .mem__1__addr( instr_mux_ch__mem__1__addr),
  .mem__1__rdata( instr_mux_ch__mem__1__rdata),
  .mem__1__wdata( instr_mux_ch__mem__1__wdata),
  .clk( clk ),
  .rstn( rstn )
);

mem_mux__11 mux_u2(
  .mem_req__0__valid( exp_mux_ch__mem_req__0__valid),
  .mem_req__0__ready( exp_mux_ch__mem_req__0__ready),
  .mem_req__0__we_n( exp_mux_ch__mem_req__0__we_n),
  .mem_req__0__addr( exp_mux_ch__mem_req__0__addr),
  .mem_req__0__rdata( exp_mux_ch__mem_req__0__rdata),
  .mem_req__0__wdata( exp_mux_ch__mem_req__0__wdata),
  .mem__0__ce_n( exp_mux_ch__mem__0__ce_n),
  .mem__0__we_n( exp_mux_ch__mem__0__we_n),
  .mem__0__addr( exp_mux_ch__mem__0__addr),
  .mem__0__rdata( exp_mux_ch__mem__0__rdata),
  .mem__0__wdata( exp_mux_ch__mem__0__wdata),
  .mem__1__ce_n( exp_mux_ch__mem__1__ce_n),
  .mem__1__we_n( exp_mux_ch__mem__1__we_n),
  .mem__1__addr( exp_mux_ch__mem__1__addr),
  .mem__1__rdata( exp_mux_ch__mem__1__rdata),
  .mem__1__wdata( exp_mux_ch__mem__1__wdata),
  .clk( clk ),
  .rstn( rstn )
);

endmodule
